1. Field of the Invention
The present invention relates to a driver/receiver circuit, and more specifically to a driver/receiver circuit comprising a driver circuit for driving a large capacitance with a small amplitude and a receiver circuit receiving an output of the driver circuit for shaping it into a signal having a large amplitude.
2. Description of Related Art
Conventionally, when a signal line interconnecting two CMOS circuits has a large capacitance, for example, when the signal line is very long, the rising and a falling of an output signal of a driver side CMOS circuit is slow. In addition, since the signal has an amplitude changing between a power supply potential and a ground potential, there was a problem that a signal transmission to a receiver side CMOS circuit took a long time. Now, the above mentioned problem of the CMOS circuit will be described with reference to FIG. 1A, which is a circuit diagram of a circuit in which each of a driver side circuit and a receiver side circuit is composed of a CMOS circuit. The driver side CMOS circuit 1 includes a P-channel MOSFET (called a "PMOS" hereinafter) 301 having its source connected to a power supply terminal V.sub.DD, its gate connected to an input terminal I and its drain connected to an output M of the driver side CMOS circuit 1, and an N-channel MOSFET (called a "NMOS" hereinafter) 302 having its source connected to a ground terminal, its gate connected to the input terminal I and its drain connected to the output M of the driver side CMOS circuit 1. The receiver side circuit 2 includes a PMOS 303 having its source connected to the power supply terminal V.sub.DD and its drain connected to an output O, and an NMOS 304 having its source connected to the ground terminal and its drain connected to the output O. Gates of the PMOS 303 and the NMOS 304 are interconnected to each other and electrically connected through a wiring. Reference Sign "CL" indicates a wiring capacitance. Both the driver side CMOS circuit 1 and the receiver side CMOS 2 function as an inverter circuit.
Next, with reference to FIG. 1B, a detailed explanation will be made as to why a delay is increased when the wiring between the driver side CMOS circuit 1 and the receiver side CMOS circuit 2 in the conventional circuit shown in FIG. 1A is long, because the wiring capacitance CL is large.
When an input signal at the input terminal I is a low level (ground level), a potential at the output terminal M of the driver side CMOS circuit 1 is at a high level (equivalent to a potential at the power supply terminal V.sub.DD), and a potential at the output terminal O of the receiver side CMOS circuit 2 is at the low level (ground level). When the input signal at the input terminal I is brought to the high level, the PMOS 301 is rendered non-conductive and the NMOS 302 is rendered conductive, so that the potential at the output terminal M of the driver side CMOS circuit 1 changes toward the ground potential in accordance with the time constant determined by a conduction resistance of the NMOS 302 and the wiring capacitance CL. The PMOS 303 of the receiver side CMOS circuit 2 changes from a non-conductive condition into a conductive condition, and the NMOS 304 of the receiver side CMOS circuit 2 changes from a conductive condition into a non-conductive condition. Here, ordinarily the receiver side CMOS circuit 1 has a circuit threshold on the order of a half of the power supply potential V.sub.DD, the potential on the output terminal O of the CMOS circuit 2 does not change until the potential of the output terminal M of the CMOS circuit 1 and the hence the gate potential of the PMOS 303 and the NMOS 304 lowers to a level less than the half of the power supply potential V.sub.DD. Thereafter, the potential of the output terminal O changes toward the power supply potential V.sub.DD, and then becomes the high level (a potential equal to the power supply potential V.sub.DD). The output signal of the CMOS circuit 1 swings from the power supply potential to the ground potential, but since the circuit threshold of the CMOS circuit 2 is at a middle between the power supply potential V.sub.DD and the ground level, the signal transmission time from the CMOS circuit 1 to the CMOS circuit 2 is in proportion to a product of the power supply potential and the wiring capacitance CL. When the power supply potential is high and CL is large, the signal transmission needs a long time. Similarly, when the input signal at the input terminal I is brought from the high level to the low level, the PMOS 301 is rendered conductive and the NMOS 302 is rendered non-conductive, so that the potential at the output terminal M of the driver side CMOS circuit 1 changes from the low level (ground potential) toward the high level (power supply potential) in accordance with the time constant determined by a conduction resistance of the PMOS 301 and the wiring capacitance CL. When the potential at the output terminal M becomes higher thorn the circuit threshold of the CMOS circuit 2, the potential at the output terminal O of the CMOS circuit 2 changes from the high level (power supply potential) toward the low level (ground potential). In this case, the time of the signal transmission from the CMOS circuit 1 to the CMOS circuit 2 is in proportion to a product of the power supply potential and the wiring capacitance CL. Accordingly, in the conventional circuit shown in FIG. 1A, where the wiring capacitance CL is large, for example, when the CMOS circuit 1 and the CMOS circuit 2 are interconnected through a long wiring, the delay in the signal transmission is very large. This was a problem.
On the other hand, since the delay in the signal transmission is in proportion to the product of the signal amplitude and the wiring capacitance as mentioned above, it is possible to reduce the delay in the signal transmission by making the signal amplitude small. A circuit shown in FIG. 2A is a conventional example in which this conception has been applied in a sense circuit for use in a memory. In FIG. 2A, a PMOS 401 has its source connected to a power supply terminal V.sub.DD, its gate connected to a ground terminal, and its drain connected to a node P. An NMOS 402 has its drain connected to the node P, its source connected to a node N, and another NMOS 403 has its drain connected to the power supply terminal V.sub.DD and its source connected to the node N. An inverter 404 has its input connected to the node N and its output connected to a gate of the NMOS 402 and a gate of the NMOS 403. An NMOS 405 has its drain connected to the node N, its gate connected to an input terminal I, and its source connected to ground.
In addition, a PMOS 406 has its source connected to the power supply terminal and its drain connected to an output terminal O, and an NMOS 407 has its drain connected to the output terminal. A PMOS 408 has its source connected to the power supply terminal V.sub.DD, and its gate connected to a drain of the PMOS 408 itself and a gate of the PMOS 406. An NMOS 9 has its drain connected to the drain of the PMOS 408, and a current source 410 is connected between a source of each of the NMOS 407 and the NMOS 409 and a ground terminal. The PMOS 406, the NMOS 407, the PMOS 408, the NMOS 409 and the current source 410 constitute a sense circuit with a reference voltage REF applied to a gate of the NMOS 409. When a potential at the node P connected to a gate of the NMOS 407 is higher than the reference voltage REF, a signal of a low level is generated at the output terminal O, and when the potential at the node P is lower than the reference voltage REF, the signal of a high level is generated at the output terminal O. A capacitance CL indicates a capacitance attributable to a long metal wiring such as a digit line of a read only memory.
An operation of the circuit shown in FIG. 2A will be described with reference to a timing chart of FIG. 2B. When a signal on the input terminal I is at a low level, a potential difference between the output and the input of the inverter 404 is equal to a threshold voltage of the NMOS 402 and the NMOS 403. Namely, the potential difference balances at a turning point which just brings the NMOS 402 and the NMOS 403 conductive or non-conductive. Thus, the node N becomes an intermediate potential realizing the above mentioned condition, and the node P is becomes equal to a potential of the power supply terminal V.sub.DD. As a result, the gate potential of the NMOS 407 is higher than the reference potential which is the gate potential of the NMOS 409, and therefore, the output terminal O becomes the high level. Next, when the signal on the input terminal I is brought from the low level to a high level, the NMOS 405 is rendered conductive, so that the potential on the node N drops. Therefore, the output potential of the inverter 404 receiving at its input the potential of the node N, namely, the gate potential of the NMOS 402 and the NMOS 403 elevates so that the NMOS 402 and the NMOS 403 are rendered conductive, and therefore, the potential on the node P quickly drops. When the potential of the node P becomes lower than the reference potential REF, the output terminal O changes to the high level. With the drop of the potential of the node N, the output of the inverter 404 elevates, and therefore, the conductive condition of the NMOS 403 becomes deep, so that a current flowing through the NMOS 403 from the power supply terminal V.sub.DD to the node N increases. Thus, the drop in the potential of the, node N stops at such a potential that the current flowing through the NMOS 403 and through the PMOS 401 and the NMOS 402 to the node N balances with a current flowing through the NMOS 405 to the ground. Therefore, the low level of the node N also becomes an intermediate potential. Accordingly, by using an NMOSFET having a large channel width as the NMOS 403 and by using a PMOSFET having a small channel width as the PMOS 401, it is possible to make the difference between the high level and the low level at the node N, namely the signal amplitude very small. When the signal on the input terminal I is brought again to the low level from the high level, the NMOS 405 is rendered non-conductive, so that the potential on the node N elevates, and therefore, the output of the inverter 404 lowers. As a result, if the potential on the node N is brought to the high level, the current no longer flows either through the NMOS 402 or through the NMOS 403. Therefore, the node P is isolated from the node N having the large capacitance CL, so that the potential on the node P rapidly elevates. Since the amplitude of the node N from the low level to the high level is small, even if the capacitance CL of the digit line is large, it is possible to bring the NMOS 402 in a substantially non-conductive condition for a short time, so that the potential on the node P is isolated from the potential of the node N. In addition, if it is so designed that a parasitic capacitance of the node P is small, even if a current driving capacity of the PMOS 401 is relatively small, it is possible to quickly elevate the potential of the node P. When the potential of the node P becomes higher than the reference potential REF, the output terminal O is brought to the low level.
The conventional circuit shown in FIG. 2A has succeeded in realizing a high speed operation even if the capacitance CL of the digit line is large, by reducing the amplitude of the signal on the node N having a large capacitance. However, the conventional circuit shown in FIG. 2A is not suitable as a driver circuit for driving a long metal wiring connecting between circuit blocks formed on a semiconductor substrate. The reason for this is that, since a large wiring capacitance is added to a wiring extending between the node P and the gate of the NMOS 407 for interconnecting between the circuit blocks but the current driving capability of the PMOS 401 is small, the delay becomes extremely large. In addition, in order to cause a signal to vibrate with a small amplitude at an intermediate potential between the power supply potential and the ground potential, as in the signal on the node N in this conventional circuit, there is formed a DC current path from the power supply terminal V.sub.DD to the ground terminal (a path passing from V.sub.DD through the NMOS 403 and the NMOS 405 to the ground when the node N is at the low level). In addition, a current constantly flows in the sense circuit composed of the PMOS 406, the NMOS 407, the PMOS 408, the NMOS 409 and the current source 410. Accordingly, this is disadvantageous because of the large amount of electric power consumed.
As mention above, in the conventional circuit shown in FIG. 1A having the driver side circuit and the receiver side circuit each composed of the CMOS circuit, when the amplitude of the output signal of the driver side circuit is large, particularly when the wiring connecting between the driver side CMOS circuit and the receiver side CMOS circuit is long and therefore has a large capacitance, the time required for the signal to change to the circuit threshold of the receiver side CMOS circuit is long, and therefore, the delay in the signal transmission is large. In addition, the conventional circuit of FIG. 1A configured to reduce the signal amplitude in a large capacitance wiring, has such a problem that it is not suitable as the driver circuit, and the amount of consumed electric power is large.